facetok EDA

Introduction

facetok EDA is an AI EDA platform for industrial-grade PCB and package design. Describe the circuit in plain language and it generates the schematic and PCB layout. Its focus is constraint closure: intelligent placement weighs topology, thermal, return path, escape feasibility and congestion prediction; BGA escape routing targets 0.3/0.4 mm pitch, phone boards, AI accelerator cards and FPGA/HBM with fan-out, dogbone, microvia and channel allocation; high-speed SerDes and DDR preserve impedance continuity, return path, via stub, skew, crosstalk and eye-diagram margin; SI, PI, RF, thermal and manufacturability constraints are handled together. It imports KiCad, Altium, Allegro, EAGLE and OrCAD projects, checks DRC and DFM in real time, and exports Gerber, BOM and IPC-2581. The engine is built on C++/Qt and Rust, and the in-house AI router combines RUDY congestion awareness, reinforcement-learning policies and tunnelling-style probabilistic search.

Screenshots

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Features

• Plain-language circuit requirements become a schematic and PCB layout via an in-house Rust AI agent
• Intelligent placement weighs topology, thermal, return path, escape feasibility and congestion prediction
• BGA escape routing covers 0.3/0.4 mm pitch, phone boards, AI accelerator cards and FPGA/HBM
• High-speed SerDes and DDR routing preserves impedance continuity, skew, crosstalk and eye-diagram margin
• Topology synthesis and system-level routing across backplane, connectors, cables and package
• Learns the implicit rules engineers carry and turns them into searchable, trade-off-aware, verifiable decisions
• Imports KiCad, Altium, Allegro, EAGLE and OrCAD project files
• Real-time DRC plus enhanced DFM for teardrops, copper pours and power plane splits
• SI, PI, RF and thermal multi-physics constraints with frequency-domain analysis
• RUDY look-ahead congestion awareness, reinforcement-learning policies and quantum-tunnelling-style exploration
• Exports Gerber, BOM, IPC-2581, ODB++, Specctra DSN and IDF